1. Field of the Invention
The present invention is related to the field of semiconductor technology, and particularly to a transistor and a method for forming the same.
2. Description of Prior Art
Stress Memorization Technique (SMT) and Stressed-contact etch stop layer (Stressed-CESL) are two solutions to promote transistor carrier mobility currently. By virtue of the two solutions, stable stress is formed in a channel region of a transistor which can promote carrier mobility in the channel. The stress is parallel to the longitudinal direction of the channel, and may be tensile stress or compressive stress. In general, the tensile stress may loosen the atomic arrangement in the channel for promoting mobility of electrons, and is adapted for NMOS transistor. The compressive stress may tighten the atomic arrangement in the channel for promoting mobility of holes, and is adapted for PMOS transistor.
FIGS. 1-3 are cross-sectional views showing a method for forming a transistor in prior art.
First, referring to FIG. 1, a semiconductor substrate 10 is provided. An NMOS transistor and a PMOS transistor are formed in the semiconductor substrate 10. An isolation structure 11 is formed between the NMOS transistor and the PMOS transistor. The NMOS transistor comprises a P well (not shown), NMOS transistor source/drain regions 12 in the P well, and an NMOS transistor gate electrode 13 on the semiconductor substrate between the NMOS transistor source/drain regions 12. The PMOS transistor comprises an N well (not shown), PMOS transistor source/drain regions 14 in the N well, and a PMOS transistor gate electrode 15 on the semiconductor substrate between the PMOS transistor source/drain regions 14.
Then, referring to FIG. 2, a stress layer 16 is formed on the NMOS transistor and the PMOS transistor, covering the NMOS transistor source/drain regions 12, the NMOS transistor gate electrode 13, and the semiconductor substrate 10. The material of the stress layer 16 can be silicon nitride. The stress layer 16 can provide tensile stress or compressive stress. Supposing the stress layer 16 provides tensile stress and has a beneficial affect on the NMOS transistor.
Then, referring to FIG. 3, through etching process using a mask layer, the stress layer 16 on the PMOS transistor is removed, while the stress layer 16 on the NMOS transistor is remained. The stress layer 16 on the NMOS transistor is annealed for providing tensile stress which stays in the NMOS transistor. The tensile stress promotes carrier (electrons) mobility in the NMOS transistor channel. After annealing, the stress layer 16 on the NMOS transistor gate electrode 13, the NMOS transistor source/drain regions 12 and the semiconductor substrate 10 are removed by etching.
However, it is found in practice that saturation current of transistors formed by conventional methods is too low and device performance is affected.